To reduce noise and the like, one layer of a conductor circuit is used as a ground layer or a power layer in a multilayer build-up wiring board having a plurality of conductor layers (conductor circuits) isolated by interlayer resin insulating layers, respectively. In the multilayer build-up wiring board, as shown in FIG. 9C, a plain layer 559 forming a ground conductor layer (ground layer) or a power conductor layer (power layer) is often formed into a mesh pattern having mesh holes 559a. The reason for providing the mesh holes 559a is as follows. Since the plain layer 559 is formed of copper having a low connection property for connecting with resin, the connection between an upper layer or an interlayer resin insulating layer (not shown) and a lower layer ora resin core substrate (not shown) is improved by directly connecting the interlayer resin insulating layer to the core substrate with the mesh holes 559a. In addition, it is intended to make it easy for gas containing moisture and the like absorbed by the interlayer resin insulating layer to exhale through the mesh holes 559a. 
As for the positions for forming these mesh hole 559a, there are various proposals made. For example, Japanese Patent Unexamined Application Publication No. 1-163634 proposes, as shown in FIG. 9B, a technique for providing the penetrating holes 559a of an upper plain layer 559 and mesh holes 559a of a lower plain layer 559B so as not to overlap one another by shifting the positions of the penetrating holes 559a of the upper plain layer 559 and those of the mesh holes 559a of the lower plain layer 559B from one another to thereby prevent recessed portions from being formed on the surface of a board.
An interlayer resin insulating layer separating conductor layers is required to have high insulating property. The inventor of the present invention discovered that the insulating property of the interlayer resin insulating layer correlates to the relative positional relationship between the penetrating holes formed on the upper and lower plain layers. Then, a multilayer build-up wiring board is formed while the positions of the penetrating holes are adjusted, and the insulating property of the interlayer resin insulating layer is measured. As a result, the present inventor reached a conclusion that if the penetrating holes 559a of the upper plain layer 559 are shifted from the mesh holes 559a of the lower plain layer 559B as shown in FIG. 9B, the insulating property of the interlayer resin insulating layer greatly deteriorates.
The present invention has been made to solve the above-stated disadvantage. One object of the present invention is to provide a multilayer build-up wiring board provided with a plain layer and having the less deterioration of the insulating property of the interlayer resin insulating layer.
Meanwhile, as for the positions at which these mesh holes are formed, various proposals have been made. For example, Japanese Patent Unexamined Application Publication No. 10-200271 proposes a technique, as shown in FIG. 23, that mesh holes are not provided in a region of a plain layer 559 facing a chip mount region indicated by C and only provided in a region outside the chip mount region, thereby preventing irregular portions from being provided in the chip mounting region to thereby make the chip mount region flat on a multilayer printed circuit board.
As stated above, gas contained in the interlayer resin insulating layer is exhaled through the mesh holes. If no mesh hole is provided in the chip mount region as in the above technique, moisture does not exhale from an interlayer resin insulating layer below the chip mount region. Then, the interlayer resin insulating layer is peeled off or the insulation resistance of the interlayer resin insulating layer deteriorates.
The present invention has been made to solve the above disadvantage and its still further object is to provide a multilayer build-up wiring board having less insulation deterioration of the interlayer resin insulating layer and capable of forming a flat chip mount region.
Meanwhile, a multilayer build-up wiring board forming a package board for mounting an IC chip and the like is formed by alternately building up interlayer resin insulating layers and conductor layers on a core board provided with through holes and by providing connection bumps for connecting to the IC chip on the upper surface side and bumps for connecting to a mother board on the lower surface side. Then, the upper and lower conductor layers are connected by forming via holes and the via holes on the upper layer of the core board and those on the lower layer thereof are connected to one another by a through hole.
However, the via holes are formed by providing non-penetrating holes in the interlayer resin insulating layers. Due to this, the number of via holes of a fixed size to be formed in the multilayer build-up wiring board is physically limited, which is one of the factors disadvantageously preventing high concentration of the via holes in the multilayer build-up wiring board.
The present invention has been made to solve the above disadvantage and its still further object is to provide a multilayer build-up wiring board capable of providing wirings with high concentration.
Further, as a technique for a multilayer build-up wiring board using a resin board, for example, Japanese Patent Examined Application Publication No. 4-55555 proposes a method of forming epoxy acrylate on a glass epoxy board, on which circuits are mounted, as interlayer resin insulating layers, providing opening portions for via holes using photolithography, roughening the surface, providing a plating resist and thereby forming conductor circuits and via holes by plating.
Conventionally, after the conductor circuits and via holes are formed by the above method, a roughened layer made of Cu—Ni—P alloy for coating the conductor circuits and the like is formed by electroless plating and an interlayer resin insulating layer is formed thereon.
However, if fabricated printed circuit boards are subjected to a heat cycle test or the like, some of them cannot be used as a multilayer build-up wiring board because cracks occur from the corners of an upper layer conductor circuit through the interlayer resin insulating layer and the cracks spread toward the upper surface of the board and a lower layer conductor circuit resulting from the difference in heat expansion between the upper layer conductor circuit made of metal and the interlayer resin insulating layer made of resin.
The reason the cracks occur is, it appears, that the corners of the upper layer conductor circuit tend to be sharpened and stress is concentrated on the corners by the expansion and compression due to the temperature change of the upper layer conductor circuit.
The present invention has been made to solve the above disadvantage of the conventional technique and a still further object is to provide a wiring board and a multilayer build-up wiring board capable of preventing the concentration of stress derived from the change of temperature of the corners of the formed conductor circuit and preventing the resin insulating layer from cracking.